1. Field of the Invention
The present invention relates generally to a method for forming a metal-oxide-semiconductor device, and more particularly to a method for avoiding the ion penetration with the plasma doping.
2. Description of the Prior Art
As semiconductor devices, such as Metal-Oxide-Semiconductor (MOS) devices, become highly integrated, the area occupied of the chip has to be maintained or more less, so as to reduce the unit cost of the circuit. For corresponding with the development of the high technology industry in the future, there is only one method to achieve this objective, that is, the area occupied by the devices shrinks, as well as the design rule. With advances in the semiconductor technology, the dimensions of the integrated circuit (IC) devices have been shrunk to the deep sub-micron range. As the semiconductor device continuously shrinks to deep submicron region, some problems are incurred due to the process of scaling down.
Metal-oxide-semiconductor (MOS) devices have been well known in the prior art. In particular, Field-effect transistors (FETs) and other related insulated-gate electronic devices are mainstay components of metal-oxide-semiconductor integrated circuits. A MOSFET generally consists of two closely spaced, doped regions in a substrate; namely, the source region and the drain region. The region between the two doped regions is the channel above which a thin insulation layer such as a gate oxide layer is formed. A gate conductor is formed from a gate material directly over the insulation layer directly above the channel and a voltage applied to the gate conductor affects the electronic properties of the channel region, whereby the MOSFET can control current flow between the source region and the drain region (e.g., is turned on and off).
As is generally well-known in the art of CMOS technology, a CMOS (complementary metal-oxide-semiconductor) device is formed of an N-channel MOS device and a P-channel MOS device, wherein the PMOS devices are formed by implanting the substrate with a p-type dopant to form heavily doped p+ source and drain regions using a self-aligned process, and the NMOS devices are formed by implanting the substrate with a n-type dopant to form heavily doped n− source and drain regions using a self-aligned process. Since the gate conductor is used in the self-aligned process, it is also implanted with a p-type/n-type dopant, for example of p-type dopant ions include B+ and BF2+. Among B+ and BF2+, BF2+ is preferred because of its larger atomic mass.
Furthermore, in order to increase the speed of the CMOS devices, there has existed in the micro-electronics industry over the last two decades an aggressive scaling-down of the channel length dimensions. However, as the channel length reduction occurs, the thickness of the gate oxide has to be likewise reduced down so as to avoid short channel effects. Thus, there has been proposed heretofore of using a p+-type polycrystalline silicon (poly-Si) gate so as to provide a surface channel feature in P-channel MOS devices in advanced CMOS structures. This is due to the fact that it is known that surface-channel P-channel MOS devices with p+-type poly-Si gates can improve short-channel and sub-threshold I-V characteristics and produce better controllability of the threshold voltage.
FIGS. 1A to 1C are cross-sectional views showing the progression of manufacturing steps in the formation of the metal-oxide-semiconductor according a conventional method. First of all, a substrate 100 is provided, and a shallow trench isolation 110 is formed in the substrate 100. Then, a gate oxide layer 120 having an uniform thickness is formed on the substrate 100 by way of a thermal oxidation process. Thereafter, a poly gate 130A is formed and defined on the gate oxide layer 120. Next, proceeding a self-aligned implanting process 140 with boron ions into the poly gate 130A and substrate 100. Afterward, a uniform ion-implanting region 150 and a poly gate 130B having a lower contact resistance are formed by way of using a thermal anneal process.
Typically, BF2+ ions are implanted simultaneously with the forming of the p+ poly-Si gate and a p+ shallow junction. In particular, when fluorine is present in a gate conductor along with boron, fluorine enhances boron penetration through the gate oxide and into the channel region during thermal anneals. Boron ions which have penetrated into the silicon substrate may cause a shift in the threshold voltage (Vth) of the operating device. This is because boron diffusion into the channel region results in a change in the concentration level of the n-channel substrate thereby causing a shift in threshold voltage and degrading the reliability of the devices oxide quality. Accordingly, the problem of boron penetration through the thin gate oxide due to scaling-down has become one of the major concerns for advanced CMOS technology. There are known in the art of various techniques which have been used for suppressing boron penetration. One such method is the use of nitrogen implantation into the p+ poly-Si gate. Another known method in the prior art is utilizing of an amorphous silicon gate. Also, still another known method involves the use of a stacked amorphous silicon/poly-Si gate. However, all of these aforementioned approaches suffer from the disadvantage of increasing the complexity of the conventional CMOS fabrication process. This is because of the different deposition process required for the poly as well as different etching processes needed to remove the poly. In view of the foregoing, there still exists a method for fabricating advanced CMOS integrated circuits so as to prevent ions penetration through the thin gate oxide of devices, which require only minimal modification to the conventional MOS fabrication process.
In accordance with the above description, a new and improved method for forming the metal-oxide-semiconductor is therefore necessary, so as to raise the yield and quality of the follow-up process.